The invention relates to an integrated CMOS circuit of the gate-array type comprising a semiconductor body provided at one surface with; a first row and an adjacent parallel second row of n-channel MOS transistors having common gate electrodes in the form of conductor tracks extending transverse to the row direction over both rows, and a first row and an adjacent parallel second row of p-channel MOS transistors having common gate electrodes in the form of conductor tracks extending transverse to the row direction over both rows. Such a device is known, for example, from U.S. Pat. No. 4,764,798.
Gate arrays offer, as is known, the possibility of keeping the period from design to manufacture of integrated circuits having a given function very short. The silicon wafers inclusive of the source and drain zones and the polysilicon generally used for the gate electrodes of the D- and p-channel MOS transistors arranged in a regular pattern are manufactured and then stored. When a given function has to be integrated on behalf of a customer, this function can be entirely implemented using the patterns of contact holes and wiring in one or more wiring layers. This means that the manufacturer need only carry out, with the wafers already available, the last stages of the manufacturing process (i.e. contact holes and wiring layers plus etching steps).
When ascertaining the size of the field effect transistors, more particularly the width thereof, a number of more or less conflicting requirements must be taken into account, which generally lead to a compromise, which is never entirely satisfactory. It should be noted that the width is to be understood to mean the dimension parallel to the surface transverse to the current direction of drain and source. For a ROM, very small transistors are sufficient, which have the advantage of a very high packing density. On the contrary, considerably larger transistors are required for given logic functions. Such transistors could be obtained in that transistors arranged consecutively in a row are connected in parallel. It has been found, however, that in practice this solution requires a very large amount of space and often strongly reduces the flexibility when designing a circuit having a given function.
The aforementioned U.S. Pat. No. 4,764,798 proposes to use instead of one row two adjacent rows of n-channel MOST's having common gate electrodes and two rows of p-channel field effect transistors having common gate electrodes. When, where desired, adjacent n-zones and p-zones, respectively, are connected to each other, transistors can be obtained having a two times larger width. Due to this configuration, a considerable increase in flexibility is obtained. It is possible more particularly to form p-channel transistors, whose channel width is two times the width of n-channel transistors, especially to compensate for the approximately two times lower mobility of holes with respect to electrons. However, in the case in which transistors are required whose channel widths have a ratio of more than 2, it is nevertheless necessary again in this configuration to connect transistors in a row in parallel.